<?xml version="1.0" encoding="utf-8"?>
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.1//EN" "http://www.w3.org/TR/xhtml11/DTD/xhtml11.dtd">
<html xmlns="http://www.w3.org/1999/xhtml">
  <head>
    <title>ID_MMFR2</title>
    <link href="insn.css" rel="stylesheet" type="text/css"/>
  </head>
  <body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h1 class="register-section">ID_MMFR2, Memory Model Feature Register 2</h1><p>The ID_MMFR2 characteristics are:</p><h2>Purpose</h2>
        <p>Provides information about the implemented memory model and memory management support in AArch32 state.</p>

      
        <p>For general information about the interpretation of the ID registers see <span class="xref">'Principles of the ID scheme for fields in ID registers'</span>.</p>
      <h2>Configuration</h2><p>AArch32 System register ID_MMFR2 bits [31:0] are architecturally mapped to AArch64 System register <a href="AArch64-id_mmfr2_el1.html">ID_MMFR2_EL1[31:0]</a>.</p><p>This register is present only when EL1 is capable of using AArch32. Otherwise, direct accesses to ID_MMFR2 are <span class="arm-defined-word">UNDEFINED</span>.</p><h2>Attributes</h2>
        <p>ID_MMFR2 is a 32-bit register.</p>
      <h2>Field descriptions</h2><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="lr" colspan="4"><a href="#fieldset_0-31_28">HWAccFlg</a></td><td class="lr" colspan="4"><a href="#fieldset_0-27_24">WFIStall</a></td><td class="lr" colspan="4"><a href="#fieldset_0-23_20">MemBarr</a></td><td class="lr" colspan="4"><a href="#fieldset_0-19_16">UniTLB</a></td><td class="lr" colspan="4"><a href="#fieldset_0-15_12">HvdTLB</a></td><td class="lr" colspan="4"><a href="#fieldset_0-11_8">L1HvdRng</a></td><td class="lr" colspan="4"><a href="#fieldset_0-7_4">L1HvdBG</a></td><td class="lr" colspan="4"><a href="#fieldset_0-3_0">L1HvdFG</a></td></tr></tbody></table><h4 id="fieldset_0-31_28">HWAccFlg, bits [31:28]</h4><div class="field">
      <p>Hardware Access Flag. In earlier versions of the Arm Architecture, this field indicates support for a Hardware Access flag, as part of the VMSAv7 implementation. Defined values are:</p>
    <table class="valuetable"><tr><th>HWAccFlg</th><th>Meaning</th></tr><tr><td class="bitfield">0b0000</td><td>
          <p>Not supported.</p>
        </td></tr><tr><td class="bitfield">0b0001</td><td>
          <p>Support for VMSAv7 Access flag, updated in hardware.</p>
        </td></tr></table><p>All other values are reserved.</p>
<p>In Armv8-A, the only permitted value is <span class="binarynumber">0b0000</span>.</p></div><h4 id="fieldset_0-27_24">WFIStall, bits [27:24]</h4><div class="field">
      <p>Wait For Interrupt Stall. Indicates the support for Wait For Interrupt (WFI) stalling. Defined values are:</p>
    <table class="valuetable"><tr><th>WFIStall</th><th>Meaning</th></tr><tr><td class="bitfield">0b0000</td><td>
          <p>Not supported.</p>
        </td></tr><tr><td class="bitfield">0b0001</td><td>
          <p>Support for WFI stalling.</p>
        </td></tr></table><p>All other values are reserved.</p>
<p>In Armv8-A, the permitted values are <span class="binarynumber">0b0000</span> and <span class="binarynumber">0b0001</span>.</p></div><h4 id="fieldset_0-23_20">MemBarr, bits [23:20]</h4><div class="field">
      <p>Memory Barrier. Indicates the supported memory barrier System instructions in the (coproc == 1111) encoding space. Defined values are:</p>
    <table class="valuetable"><tr><th>MemBarr</th><th>Meaning</th></tr><tr><td class="bitfield">0b0000</td><td>
          <p>None supported.</p>
        </td></tr><tr><td class="bitfield">0b0001</td><td><p>Supported memory barrier System instructions are:</p>
<ul>
<li>Data Synchronization Barrier (DSB).
</li></ul></td></tr><tr><td class="bitfield">0b0010</td><td><p>As for <span class="binarynumber">0b0001</span>, and adds:</p>
<ul>
<li>Instruction Synchronization Barrier (ISB).
</li><li>Data Memory Barrier (DMB).
</li></ul></td></tr></table><p>All other values are reserved.</p>
<p>In Armv8-A, the only permitted value is <span class="binarynumber">0b0010</span>.</p>
<p>Arm deprecates the use of these operations. <a href="AArch32-id_isar4.html">ID_ISAR4</a>.Barrier_instrs indicates the level of support for the preferred barrier instructions.</p></div><h4 id="fieldset_0-19_16">UniTLB, bits [19:16]</h4><div class="field">
      <p>Unified TLB. Indicates the supported TLB maintenance operations, for a unified TLB implementation. Defined values are:</p>
    <table class="valuetable"><tr><th>UniTLB</th><th>Meaning</th></tr><tr><td class="bitfield">0b0000</td><td>
          <p>Not supported.</p>
        </td></tr><tr><td class="bitfield">0b0001</td><td><p>Supported unified TLB maintenance operations are:</p>
<ul>
<li>Invalidate all entries in the TLB.
</li><li>Invalidate TLB entry by VA.
</li></ul></td></tr><tr><td class="bitfield">0b0010</td><td><p>As for <span class="binarynumber">0b0001</span>, and adds:</p>
<ul>
<li>Invalidate TLB entries by ASID match.
</li></ul></td></tr><tr><td class="bitfield">0b0011</td><td><p>As for <span class="binarynumber">0b0010</span>, and adds:</p>
<ul>
<li>Invalidate instruction TLB and data TLB entries by VA All ASID. This is a shared unified TLB operation
</li></ul></td></tr><tr><td class="bitfield">0b0100</td><td><p>As for <span class="binarynumber">0b0011</span>, and adds:</p>
<ul>
<li>Invalidate Hyp mode unified TLB entry by VA.
</li><li>Invalidate entire Non-secure PL1&amp;0 unified TLB.
</li><li>Invalidate entire Hyp mode unified TLB.
</li></ul></td></tr><tr><td class="bitfield">0b0101</td><td>
          <p>As for <span class="binarynumber">0b0100</span>, and adds the following operations: <a href="AArch32-tlbimvalis.html">TLBIMVALIS</a>, <a href="AArch32-tlbimvaalis.html">TLBIMVAALIS</a>, <a href="AArch32-tlbimvalhis.html">TLBIMVALHIS</a>, <a href="AArch32-tlbimval.html">TLBIMVAL</a>, <a href="AArch32-tlbimvaal.html">TLBIMVAAL</a>,<a href="AArch32-tlbimvalh.html">TLBIMVALH</a>.</p>
        </td></tr><tr><td class="bitfield">0b0110</td><td>
          <p>As for <span class="binarynumber">0b0101</span>, and adds the following operations: <a href="AArch32-tlbiipas2is.html">TLBIIPAS2IS</a>, <a href="AArch32-tlbiipas2lis.html">TLBIIPAS2LIS</a>, <a href="AArch32-tlbiipas2.html">TLBIIPAS2</a>, <a href="AArch32-tlbiipas2l.html">TLBIIPAS2L</a>.</p>
        </td></tr></table><p>All other values are reserved.</p>
<p>In Armv8-A, the only permitted value is <span class="binarynumber">0b0110</span>.</p></div><h4 id="fieldset_0-15_12">HvdTLB, bits [15:12]</h4><div class="field">
      <p>If the value of ID_MMFR2.UniTLB is not <span class="binarynumber">0b0000</span>, then the meaning of this field is <span class="arm-defined-word">IMPLEMENTATION DEFINED</span>. Arm deprecates the use of this field by software.</p>
    </div><h4 id="fieldset_0-11_8">L1HvdRng, bits [11:8]</h4><div class="field">
      <p>Level 1 Harvard cache Range. Indicates the supported Level 1 cache maintenance range operations, for a Harvard cache implementation. Defined values are:</p>
    <table class="valuetable"><tr><th>L1HvdRng</th><th>Meaning</th></tr><tr><td class="bitfield">0b0000</td><td>
          <p>Not supported.</p>
        </td></tr><tr><td class="bitfield">0b0001</td><td><p>Supported Level 1 Harvard cache maintenance range operations are:</p>
<ul>
<li>Invalidate data cache range by VA.
</li><li>Invalidate instruction cache range by VA.
</li><li>Clean data cache range by VA.
</li><li>Clean and invalidate data cache range by VA.
</li></ul></td></tr></table><p>All other values are reserved.</p>
<p>In Armv8-A, the only permitted value is <span class="binarynumber">0b0000</span>.</p></div><h4 id="fieldset_0-7_4">L1HvdBG, bits [7:4]</h4><div class="field">
      <p>Level 1 Harvard cache Background fetch. Indicates the supported Level 1 cache background fetch operations, for a Harvard cache implementation. When supported, background fetch operations are non-blocking operations. Defined values are:</p>
    <table class="valuetable"><tr><th>L1HvdBG</th><th>Meaning</th></tr><tr><td class="bitfield">0b0000</td><td>
          <p>Not supported.</p>
        </td></tr><tr><td class="bitfield">0b0001</td><td><p>Supported Level 1 Harvard cache background fetch operations are:</p>
<ul>
<li>Fetch instruction cache range by VA.
</li><li>Fetch data cache range by VA.
</li></ul></td></tr></table><p>All other values are reserved.</p>
<p>In Armv8-A, the only permitted value is <span class="binarynumber">0b0000</span>.</p></div><h4 id="fieldset_0-3_0">L1HvdFG, bits [3:0]</h4><div class="field">
      <p>Level 1 Harvard cache Foreground fetch. Indicates the supported Level 1 cache foreground fetch operations, for a Harvard cache implementation. When supported, foreground fetch operations are blocking operations. Defined values are:</p>
    <table class="valuetable"><tr><th>L1HvdFG</th><th>Meaning</th></tr><tr><td class="bitfield">0b0000</td><td>
          <p>Not supported.</p>
        </td></tr><tr><td class="bitfield">0b0001</td><td><p>Supported Level 1 Harvard cache foreground fetch operations are:</p>
<ul>
<li>Fetch instruction cache range by VA.
</li><li>Fetch data cache range by VA.
</li></ul></td></tr></table><p>All other values are reserved.</p>
<p>In Armv8-A, the only permitted value is <span class="binarynumber">0b0000</span>.</p></div><div class="access_mechanisms"><h2>Accessing ID_MMFR2</h2><p>Accesses to this register use the following encodings in the System register encoding space:</p><h4 class="assembler">MRC{&lt;c&gt;}{&lt;q&gt;} &lt;coproc&gt;, {#}&lt;opc1&gt;, &lt;Rt&gt;, &lt;CRn&gt;, &lt;CRm&gt;{, {#}&lt;opc2&gt;}</h4><table class="access_instructions"><tr><th>coproc</th><th>opc1</th><th>CRn</th><th>CRm</th><th>opc2</th></tr><tr><td>0b1111</td><td>0b000</td><td>0b0000</td><td>0b0001</td><td>0b110</td></tr></table><p class="pseudocode">
if PSTATE.EL == EL0 then
    UNDEFINED;
elsif PSTATE.EL == EL1 then
    if EL2Enabled() &amp;&amp; !ELUsingAArch32(EL2) &amp;&amp; HSTR_EL2.T0 == '1' then
        AArch64.AArch32SystemAccessTrap(EL2, 0x03);
    elsif EL2Enabled() &amp;&amp; ELUsingAArch32(EL2) &amp;&amp; HSTR.T0 == '1' then
        AArch32.TakeHypTrapException(0x03);
    elsif EL2Enabled() &amp;&amp; !ELUsingAArch32(EL2) &amp;&amp; HCR_EL2.TID3 == '1' then
        AArch64.AArch32SystemAccessTrap(EL2, 0x03);
    elsif EL2Enabled() &amp;&amp; ELUsingAArch32(EL2) &amp;&amp; HCR.TID3 == '1' then
        AArch32.TakeHypTrapException(0x03);
    else
        R[t] = ID_MMFR2;
elsif PSTATE.EL == EL2 then
    R[t] = ID_MMFR2;
elsif PSTATE.EL == EL3 then
    R[t] = ID_MMFR2;
                </p></div><hr class="bottom_line"/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">30/03/2023 19:07; 997dd0cf3258cacf72aa7cf7a885f19a4758c3af</p><p class="copyconf">Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.</p></body>
</html>
